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single-phase high-performance wide-span energy metering ic 90E21/22/23/24 version 6 january 10, 2012 6024 silver creek valley road, san jose, ca 95138 printed in u.s.a. ? 2012 integrated device technology, inc.
disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best pos- sible product. idt does not assume any res ponsibility for use of any circuitry described other than the circuitry embodied in a n idt product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent, pat ent rights or other rights, of integrated device technology, inc. life support policy integrated device technology's products ar e not authorized for use as critical com ponents in life support devices or systems un less a specific written agr eement pertaining to such intended use is exe- cuted between the manufacture r and an officer of idt. 1. life support devices or systems are devices or systems whic h (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose fa ilure to perform can be reasonably expecte d to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness.
table of contents 3 january 10, 2012 features ............. ................. ................ ................. .............. .............. .............. .............. ................. .............. .............. .......... 6 application ............. ................ ................. .............. .............. .............. ............... ............. .................... .............. ............ ....... 6 description............. ................ ................. .............. .............. .............. ............... ............. .................... .............. ............ ....... 6 block diagram .................. ................ ................. ................ ................. ................ .............. ............... .............. ............ ....... 7 1 pin assignment ....... ................ ................. .............. .............. .............. ............... .............. ................ ................. ............. 9 2 pin description ........... ................ ................. ................ ................. ................ ................. ................ ................. ........... 10 3 functional description ............... ................ ................. .............. .............. .............. ............. ............. ............ ......... 12 3.1 dynamic metering range ..................................................................................................... ............................................................... 12 3.2 startup and no-load power .................................................................................................. ........................................................... 12 3.3 energy registers ........................................................................................................... ....................................................................... 12 3.4 n line metering and anti-tampering ......................................................................................... ..................................................... 13 3.4.1 metering mode and l/n line curr ent sampling gain configuration ........................................................... .............................. 13 3.4.2 anti-tampering mode ...................................................................................................... .............................................................. 13 3.5 measurement and zero-crossing .............................................................................................. ..................................................... 14 3.5.1 measurement .............................................................................................................. .................................................................... 14 3.5.2 zero-crossing ............................................................................................................ ..................................................................... 14 3.6 calibration ................................................................................................................ .............................................................................. 15 3.7 reset ...................................................................................................................... ..................................................................................... 15 4 interface ............ ................. ................ .............. ............... .............. .............. .............. .............. .............. ............ ......... 16 4.1 serial peripheral interface (spi) .......................................................................................... ......................................................... 16 4.1.1 four-wire mode ........................................................................................................... ................................................................... 16 4.1.2 three-wire mode .......................................................................................................... .................................................................. 17 4.1.3 timeout and protection ................................................................................................... .............................................................. 18 4.2 warnout pin for fata l error warning ........................................................................................ ............................................... 18 4.3 low cost implementation in isolation with mcu .............................................................................. ........................................ 18 5 register ............. ................ ................. .............. .............. .............. ............... .............. ................ .............. ............ ......... 19 5.1 register list .............................................................................................................. .............................................................................. 19 5.2 status and special register ................................................................................................ ............................................................ 21 5.3 metering/ measurement cali bration and configuration ........................................................................ ............................ 25 5.3.1 metering calibration and configuration register .......................................................................... ............................................. 25 5.3.2 measurement calibration register ......................................................................................... ...................................................... 32 5.4 energy register ............................................................................................................ ........................................................................ 37 5.5 measurement register ....................................................................................................... ................................................................ 41 6 electrical specificatio n .................. .............. .............. .............. .............. .............. ............. ............. ............ ......... 48 6.1 electrical specification ................................................................................................... ................................................................ 48 6.2 spi interface timing ....................................................................................................... ....................................................................... 50 6.3 power on reset timing ...................................................................................................... .................................................................. 51 6.4 zero-crossing timing ....................................................................................................... .................................................................... 51 6.5 voltage sag timing ......................................................................................................... ...................................................................... 52 6.6 pulse output ............................................................................................................... ............................................................................ 52 6.7 absolute maximum rating .................................................................................................... .............................................................. 53 package dimensions............ ................. ................ ................. ................ ................. .............. ................. .............. .......... 54 ordering information........ ................. ................ ................. ................ ................. ................ ............... .............. .......... 57 table of contents
list of tables 4 january 10, 2012 table-1 function list ........................................................................................................ ........................................................................................... 6 table-2 pin description ...................................................................................................... ....................................................................................... 10 table-3 active energy metering error ......................................................................................... .............................................................................. 12 table-4 reactive energy metering error ....................................................................................... ............................................................................ 12 table-5 threshold configurati on for startup and no-load power ................................................................ ............................................................ 12 table-6 energy registers ..................................................................................................... .................................................................................... 12 table-7 metering mode ........................................................................................................ ..................................................................................... 13 table-8 the measurement format ............................................................................................... ............................................................................ 14 table-9 read / write result in four-wire mode ................................................................................ ....................................................................... 18 table-10 read / write result in three-wire mode .............................................................................. ....................................................................... 18 table-11 register list ....................................................................................................... .......................................................................................... 19 table-12 spi timing specification ............................................................................................ .................................................................................. 50 table-13 power on reset specification ........................................................................................ ............................................................................. 51 table-14 zero-crossing specification ......................................................................................... ................................................................................ 52 table-15 voltage sag specification ........................................................................................... ................................................................................. 52 list of tables
list of figures 5 january 10, 2012 figure-1 90E21 block diagram ................................................................................................. ................................................................................... 7 figure-2 90e22 block diagram ................................................................................................. ................................................................................... 7 figure-3 90e23 block diagram ................................................................................................. ................................................................................... 8 figure-4 90e24 block diagram ................................................................................................. ................................................................................... 8 figure-5 pin assignment (top view) ........................................................................................... ................................................................................. 9 figure-6 read sequence in four-wire mode ..................................................................................... ....................................................................... 16 figure-7 write sequence in four-wire mode .................................................................................... ......................................................................... 16 figure-8 read sequence in three-wire mode .................................................................................... ...................................................................... 17 figure-9 write sequence in three-wire mode ................................................................................... ........................................................................ 17 figure-10 4-wire spi timing diagram .......................................................................................... ............................................................................... 50 figure-11 3-wire spi timing diagram .......................................................................................... ............................................................................... 50 figure-12 power on reset timing diagram ...................................................................................... .......................................................................... 51 figure-13 zero-crossing timing diagram ....................................................................................... ............................................................................ 51 figure-14 voltage sag timing diagram ......................................................................................... ............................................................................. 52 figure-15 output pulse width ................................................................................................. .................................................................................... 52 list of figures
6 january 10, 2012 90E21/22/23/24 ? 2012 integrated device technology, inc. dsc-7277/6 single-phase high-performance wide-span energy metering ic idt and the idt logo are trademarks of integrated device technology, inc. features metering features ? metering features fully in compliance with the requirements of iec62052-11, iec62053-21 and iec62053-23; applicable in class 1 or class 2 single-phase wa tt-hour meter or class 2 single- phase var-hour meter. ? accuracy of 0.1% for active energy and 0.2% for reactive energy over a dynamic range of 5000:1. ? temperature coefficient is 15 ppm/ (typical) for on-chip refer- ence voltage ? single-point calibration over a dynamic range of 5000:1 for active energy; no calibrati on needed for reactive energy. ? energy meter constant doubling at low current to save verifica- tion time. ? electrical parameters m easurement: less than 0.5% fiducial error for vrms, irms, mean active/ reactive/ apparent power, fre- quency, power factor and phase angle. ? forward/ reverse active/ reactive energy with independent energy registers. active/ reacti ve energy can be output by pulse or read through energy registers to adapt to different applica- tions. ? programmable startup and no-load power threshold. ? dedicated adc and different gains for l line and n line current sampling circuits. current sampled over shunt resistor or current transformer (ct); voltage sampled over resistor divider network or potential transformer (pt). ? programmable l line and n line metering modes: anti-tampering mode (larger power), l line mode (fixed l line), l+n mode (appli- cable for single-phase three-wi re system) and flexible mode (configure through register). ? programmable l line and n line po wer difference threshold in anti-tampering mode. other features ? 3.3v single power supply. oper ating voltage range: 2.8~3.6v. metering accuracy guaranteed within 3.0v~3.6v. 5v compatible for digital input. ? built-in hysteresis for power-on reset. ? four-wire spi interface or simplif ied three-wire spi interface with fixed 24 cycles for al l registers operation ? parameter diagnosis function and programmable interrupt output of the irq interrupt signal and the warnout signal. ? programmable voltage sag detection and zero-crossing output. ? channel input range - voltage channel (when gain is '1'): 120 vrms~600mvrms. - l line current channel (when gain is '24'): 5 vrms~25mvrms. - n line current channel (when gain is '1'): 120 vrms~600mvrms. ? programmable l line current gain: 1, 4, 8, 16, 24; programmable n line gain: 1, 2, 4. ? support l line and n line offset compensation. ? cf1 and cf2 output active and reactive energy pulses respec- tively which can be used for cali bration or energy accumulation. ? crystal oscillator frequency: 8.192 mhz. on-chip 10pf capaci- tors and no need of external capacitors. ? green ssop28 package. ? operating temperature: -40 ~ +85 . application ? the 90E21/22/23/24 series are used for active and reactive energy metering for single-phase two-wire, single-phase three- wire or anti-tampering energy meters. with the measurement function, the 90E21/22/23/24 series can also be used in power instruments which need to measure voltage, current, etc. description the 90E21/22/23/24 series are high-performance wide-span energy metering chips. idt's proprietary adc and dsp technology ensure the chips' long-term stability over vari ations in grid and ambient environmen- tal conditions. 90E21/22/23/24 are all of green ssop28 package with the same pin alignment. in this datasheet, all reactive energy metering parts are only applicable for the 90e22/24, and all n line metering and measurement parts are only applicable for the 90e23/24. table-1 function list part number active energy metering reactive energy metering n line metering electrical parameters measurement 90E21 ? 90e22 ? 90e23 ?? 90e24 ???
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c block diagram 7 january 10, 2012 block diagram figure-1 90E21 block diagram figure-2 90e22 block diagram reference voltage power on reset crystal oscillator 3-wire or 4-wire spi vref i1p i1n vp vn l line forward/reverse active power l line apparent power l line irms vrms cs sclk sdo sdi osci osco reset ? adc ? adc hpf1 hpf0 dsp module pga x1/x4/x8/ x16/x24 pga x1 active energy pulse output cf1 hpf1 hpf0 power factor/ angle/frequency warnout/irq/zx zx irq warnout reference voltage power on reset crystal oscillator 3-wire or 4-wire spi vref i1p i1n vp vn l line forward/reverse active/ reactive power l line apparent power l line irms vrms cs sclk sdo sdi osci osco reset ? adc ? adc hpf1 hpf0 dsp module pga x1/x4/x8/ x16/x24 pga x1 active energy pulse output reactive energy pulse output cf1 cf2 hpf1 hpf0 power factor/ angle/frequency warnout/irq/zx zx irq warnout
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c block diagram 8 january 10, 2012 figure-3 90e23 block diagram figure-4 90e24 block diagram reference voltage power on reset crystal oscillator 3-wire or 4-wire spi vref i1p i1n vp vn l line forward/reverse active power l line apparent power l line irms vrms i2p i2n mmd1 mmd0 cs sclk sdo sdi osci osco reset ? adc ? adc hpf1 hpf0 dsp module pga x1/x4/x8/ x16/x24 pga x1 ? adc pga x1/x2/x4 active energy pulse output cf1 hpf1 hpf0 hpf1 hpf0 n line forward/reverse active power n line apparent power n line irms power factor/ angle/frequency warnout/irq/zx zx irq warnout reference voltage power on reset crystal oscillator 3-wire or 4-wire spi vref i1p i1n vp vn l line forward/reverse active/ reactive power l line apparent power l line irms vrms i2p i2n mmd1 mmd0 cs sclk sdo sdi osci osco reset ? adc ? adc hpf1 hpf0 dsp module pga x1/x4/x8/ x16/x24 pga x1 ? adc pga x1/x2/x4 active energy pulse output reactive energy pulse output cf1 cf2 hpf1 hpf0 hpf1 hpf0 n line forward/reverse active/ reactive power n line apparent power n line irms power factor/ angle/frequency warnout/irq/zx zx irq warnout
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c pin assignment 9 january 10, 2012 1 pin assignment figure-5 pin assignment (top view) note 1: pin 1 and 28 are dedicated for the 90e23/24. pin 1 should c onnect to dgnd and pin 28 should connect to dvdd for 90E21/22. note 2: pin 7 and 8 are dedicated for the 90e23/24. they should be left open for the 90E21/22. note 3: pin 19 is dedicated for the 90e22/24. it should be left open for the 90E21/23. 1 note 1 2 3 4 5 6 7 note 2 8 note 2 9 10 11 12 13 14 15 16 17 18 19 note 3 20 21 22 23 24 25 26 27 28 note 1 reset dvdd avdd agnd i1p i1n i2p i2n vp vn vref agnd nc warnout cs sclk sdo sdi dgnd mmd1 mmd0 osci osco nc cf1 cf2 zx irq
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c pin description 10 january 10, 2012 2 pin description table-2 pin description name pin no. i/o note 1 type description reset 4 i lvttl reset : reset pin (active low) this pin should connect to ground through a 0.1 f filter capacitor. in application it can also directly connect to one output pin from microcontroller (mcu). dvdd 3 i power dvdd: digital power supply this pin provides power supply to the digital part. it should be decoupled with a 10 f electro- lytic capacitor and a 0.1 f capacitor. dgnd 2 i power dgnd: digital ground avdd 5 i power avdd: analog power supply this pin provides power supply to the analog part. this pin should connect to dvdd through a 10 ? resistor and be decoupled with a 0.1 f capacitor. vref 13 o analog vref: output pin for reference voltage this pin should be decoupled with a 1 f capacitor and a 1nf capacitor. agnd 6, 14 i power agnd: analog ground i1p i1n 10 11 i analog i1p: positive input for l line current i1n: negative input for l line current these pins are differential inputs for l line current. input range is 5 vrms ~ 25mvrms when gain is '24'. i2p i2n 7 8 i analog i2p: positive input for n line current i2n: negative input for n line current these pins are differential inputs for n line current. input range is 120 vrms ~ 600mvrms when gain is '1'. note: i2p and i2n are dedicated for the 90e23/24. they should be left open for the 90E21/ 22. vp vn 16 15 i analog vp: positive input for voltage vn: negative input for voltage these pins are differential inputs for voltage. input range is 120 vrms ~ 600mvrms. nc 9, 12 nc: this pin should be left open. cs 24 i lvttl cs : chip select (active low) in 4-wire spi mode, this pin must be driven from high to low for each read/write operation, and maintain low for the entire operation. in 3-wire spi mode, this pin must be low all the time. refer to section 4.1 . sclk 25 i lvttl sclk: serial clock this pin is used as the clock for the spi interface. data on sdi is shifted into the chip on the rising edge of sclk while data on sdo is shifted out of the chip on the falling edge of sclk. sdo 26 oz lvttl sdo: serial data output this pin is used as the data output for the spi interface. data on this pin is shifted out of the chip on the falling edge of sclk. sdi 27 i lvttl sdi: serial data input this pin is used as the data input for the spi interface. address and data on this pin is shifted into the chip on the rising edge of sclk. mmd1 mmd0 1 28 i lvttl mmd1/0: metering mode configuration 00: anti-tampering mode (larger power); 01: l line mode (fixed l line); 10: l+n mode (applicable for single-phase three-wire system); 11: flexible mode (line specified by the lnsel bit ( mmode , 2bh)) note: the mmd1/0 pins are dedicated for the 90e23/24. for the 90E21/22, the metering mode is fixed as l line mode, and mmd1 should connect to dgnd and mmd0 should con- nect to dvdd.
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c pin description 11 january 10, 2012 osci 22 i lvttl osci: external crystal input an 8.192 mhz crystal is connected between osci and osco. there is an on-chip 10pf capacitor, therefore no need of external capacitors. osco 23 o lvttl osco: external crystal output an 8.192 mhz crystal is connected between osci and osco. there is an on-chip 10pf capacitor, therefore no need of external capacitors. cf1 cf2 18 19 o lvttl cf1: active energy pulse output cf2: reactive energy pulse output these pins output active/reactive energy pulses. note: cf2 is dedicated for the 90e22/24. it should be left open for the 90E21/23. zx 21 o lvttl zx: voltage zero-crossing output this pin is asserted when voltage crosses zero. zero-crossing mode can be configured to positive zero-crossing, negative zero-crossing or all zero-crossing by the zxcon[1:0] bits ( mmode , 2bh). irq 20 o lvttl irq: interrupt output this pin is asserted when one or more events in the sysstatus register (01h) occur. it is deasserted when there is no bit set in the sysstatus register (01h). warnout 17 o lvttl warnout: fatal error warning this pin is asserted when there is metering parameter calibration error or voltage sag. refer to section 4.2 . note 1: all digital inputs are 5v tolerant except for the osci pin. table-2 pin description (continued) name pin no. i/o note 1 type description
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c functional description 12 january 10, 2012 3 functional description 3.1 dynamic me tering range accuracy is 0.1% for active energy metering and 0.2% for reactive energy metering over a dynamic r ange of 5000:1 (typical). refer to table-3 and table-4 . 3.2 startup and no-load power startup and no-load power threshol ds are programmable, both for active and reactive power. the related registers are listed in table-5 . the chip will start within 1.2 times of the theoretical startup time of the configured startup power, if startup power is less than the corre- sponding power of 20ma when power factor or sin is 1.0. the chip has no-load status bits , the pnoload/qnoload bit (enstatus, 46h). the chip will not output any active pulse (cf1) in active no-load state. the chip will not output any reactive pulse (cf2) in reactive no- load state. 3.3 energy registers the 90E21/22/23/24 provides energy pulse output cfx (cf1/cf2) which is proportionate to active/reacti ve energy. energy is usually accu- mulated by adding the cfx pulses in system applications. alternatively, the 90E21/22/23/24 provides energy registers. there are forward (inductive), reverse (capacitive) and absolute energy registers for both active and reactive energy. refer to table-6 . each energy register is cleared a fter read. the resolution of energy registers is 0.1cf, i.e. one l sb represents 0.1 energy pulse. table-3 active energy metering error current power factor error (%) 20ma i 50ma 1.0 0.2 50ma i 100a 0.1 50ma i 100ma 0.5 (inductive) 0.8 (capacitive) 0.2 100ma i 100a 0.1 note: shunt resistor is 250 ? or ct ratio is 1000:1 and load resistor is 6 ? . table-4 reactive energy metering error current sin (inductive or capacitive) error ( % ) 20ma i 50ma 1.0 0.4 50ma i 100a 0.2 50ma i 100ma 0.5 0.4 100ma i 100a 0.2 note: shunt resistor is 250 ? or ct ratio is 1000:1 and load resistor is 6 ? . table-5 threshold configuration for startup and no-load power threshold register threshold for active startup power pstartth , 27h threshold for active no-load power pnolth , 28h threshold for reactive startup power qstartth , 29h threshold for reactive no-load power qnolth , 2ah table-6 energy registers energy register forward active energy apenergy , 40h reverse active energy anenergy , 41h absolute active energy atenergy , 42h forward (inductive) reactive energy rpenergy , 43h reverse (capacitive) reactive energy rnenergy , 44h absolute reactive energy rtenergy , 45h
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c functional description 13 january 10, 2012 3.4 n line metering and anti-tampering 3.4.1 metering mode and l/n line current sampling gain configuration the 90e23 and 90e24 have two current sampling circuits with n line metering and anti-tampering func tions. the mmd1 and mmd0 pins are used to configure the metering mode. refer to table-7 . the 90e23 and 90e24 have two current sa mpling circuits with differ- ent gain configurations. l line gain can be 1, 4, 8, 16 and 24, and n line gain can be 1, 2 and 4. the c onfiguration is made by the mmode register (2bh). generally l line can be sampled over shunt resistor or ct. n line can be sampled over ct for isolation consideration. note that rogowski coil is not supported. 3.4.2 anti-tampering mode threshold in anti-tampering mode, the power difference threshold between l line and n line can be: 1%, 2%,... 12%, 12.5%, 6.25%, 3.125% and 1.5625%, altogether 16 choices. the configuration is made by the pthresh[3:0] bits ( mmode , 2bh) and the default value is 3.125%. the threshold is applicable for active energy. the metering line of the reac- tive energy follows that of the active energy. compare method in anti-tampering mode, the compare method is as follows: if current metering line is l line and n line is switched as the metering line, otherwise l line keeps as the metering line. if current metering line is n line and l line is switched as the metering li ne, otherwise n line keeps as the metering line. this method can achieve hysteres is around the threshold automati- cally. l line is employed after reset by default. special treatment at low power when power is low, general factors such as the quantization error or calibration difference between l li ne and n line might cause the power difference to be exceeded. to ensure l line and n line to start up nor- mally, special treatment as follows is adopted: the line with higher power is sele cted as the metering line when both l line and n line power are lower than 8 times of the startup power but higher than the startup power. table-7 metering mode mmd1 mmd0 metering mode cfx (cf1 or cf2) output 00 anti-tampering mode (larger power) cfx represents the larger energy line. refer to section 3.4.2 . 0 1 l line mode (fixed l line) cfx represents l line energy all the time. 10 l+n mode (applicable for single-phase three-wire system) cfx represents the arithmetic sum of l line and n line energy 11 flexible mode (line speci- fied by the lnsel bit ( mmode , 2bh)) cfx represents energy of the specified line. threshold 100% * power active line l power active line l - power active line n > threshold 100% * power active line n power active line n - power active line l >
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c functional description 14 january 10, 2012 3.5 measurement and zero-crossing 3.5.1 measurement the 90E21/22/23/24 has the following measurements: ? voltage rms ? current rms (l line/n line) ? mean active power (l line/n line) ? mean reactive power (l line/n line) ? voltage frequency ? power factor (l line/n line) ? phase angle between voltage and current (l line/n line) ? mean apparent power (l line/n line) the above measurements are all calc ulated with fiducial error except for frequency. the frequency accuracy is 0.01hz, and the other mea- surement accuracy is 0.5%. fiduci al error is calculated as follow: where u mea is the measured voltage, u real is the actual voltage and u fv is the fiducial value. 3.5.2 zero-crossing the zx pin is asserted when the sampling voltage crosses zero. zero-crossing mode can be configured to positive zero-crossing, nega- tive zero-crossing and all zero-crossing by the zxcon[1:0] bits ( mmode , 2bh). refer to section 6.4 . the zero-crossing signal can facilita te operations such as relay oper- ation and power line carrier transmiss ion in typical smart meter applica- tions. 100% * u u - u rror fiducial_e fv real mea = table-8 the measurement format measurement fiducial value (fv) 90E21/22/23/24 defined format range comment voltage rms un xxx.xx 0~655.35v current rms note 1, note 2 imax as 4ib xx.xxx 0~65.535a active/ reactive power note 1 maximum power as un*4ib xx.xxx -32.768~+32.767 kw/kvar complement, msb as the sign bit apparent power note 1 un*4ib xx.xxx 0~+32.767 kva complement, msb always '0' frequency fn xx.xx 45.00~65.00 hz power factor note 3 1.000 x.xxx -1.000~+1.000 signed, msb as the sign bit phase angle note 4 180 xxx.x -180~+180 signed, msb as the sign bit note 1: all registers are of 16 bits. for cases when the current and active/reactive/apparent power goes beyond the above range, it is suggested to be handled by microcontroller (mcu) in application. for example, register value can be calibrated to 1/2 of the actual value during calibrati on, then multiply 2 in application. note that if the actual current is twice of that of the 90E21/22/23/24, th e actual active/reactive/apparent power is also twice of that o f the chip. note 2: the accuracy is not guaranteed when the current is lower than 15ma. note that the tolerance is 25 ma at i fv of 5a and fiducial accuracy of 0.5%. note 3: power factor is obtained by active power dividing apparent power note 4: phase angle is obtained when voltage/current crosses zero at the frequency of 256khz. precision is not guaranteed at small cur rent.
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c functional description 15 january 10, 2012 3.6 calibration metering calibration only single-point calibration is needed over the entire dynamic range. metering calibration is realized by first calibrating gain at unity power factor and then calibrating phase angle compensation at 0.5 inductive power factor. however, due to very small signal in l line current sampling circuits, any external interference, e.g., a tens of nano volts influence voltage on shunt resistor conducted by transformer in the energy meter?s power supply may cause perceptible metering error, especially in low current state. for this nearly constant external interference, the 90E21/22/23/24 also provides power offset compensation. l line and n line need to be calibrated sequentially. reactive does not need to be calibrated. measurement calibration measurement calibration is realized by calibrating the gains for volt- age rms and current rms. considering the possible nonlinearity around zero caused by external components, the chip also provides offset com- pensation for voltage rms, current rms, mean active power and mean reactive power. frequency, phase angle and power factor do not need calibration. for more calibration details, please refer to application note an-641. 3.7 reset the 90E21/22/23/24 has an on-chip power supply monitor circuit with built-in hysteresis. the 90E21/22/23/24 only works within the voltage range. the 90E21/22/23/24 has three means of reset: power-on reset, hard- ware reset and software reset. all r egisters resume to their default value after reset. power-on reset: power-on reset is initiated during power-up. refer to section 6.3. hardware reset: hardware reset is initiated when the reset pin is pulled low. the width of the reset signal should be over 200 s. software reset: software reset is initiated when ?789ah? is written to the software reset register ( softreset , 00h).
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c interface 16 january 10, 2012 4interface 4.1 serial peripheral interface (spi) spi is a full-duplex, synchronous ch annel. there are two spi modes: four-wire mode and three-wire mode. in four-wire mode, four pins are used: cs , sclk, sdi and sdo. in three-wire mode, three pins are used: sclk, sdi and sdo. data on sdi is shifted into the chip on the rising edge of sclk while data on sdo is shifted out of the chip on the falling edge of sclk. the lastspidata register (06h) stores the 16-bit data that is just read or written. 4.1.1 four-wire mode in four-wire mode, the cs pin must be driven low for the entire read or write operation. the first bit on sdi defines the access type and the lower 7-bit is decoded as address. read sequence as shown in figure-6 , a read operation is initiated by a high on sdi followed by a 7-bit register address. a 16-bit data in this register is then shifted out of the chip on sdo. a complete read operation contains 24 cycles. figure-6 read sequence in four-wire mode write sequence as shown in figure-7 , a write operation is initiated by a low on sdi followed by a 7-bit register addres s. a 16-bit data is then shifted into the chip on sdi. a complete write operation contains 24 cycles. figure-7 write sequence in four-wire mode cs sclk sdi sdo 10 123456789 111213141516171819202122 24 a0 a6 a5 a4 a3 a2 a1 register address high impedance d15 don't care d0 16-bit data 23 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 cs sclk sdi sdo 10 123456789 11121314151617181920212223 a0 a6 a5 a4 a3 a2 a1 16-bit data high impedance d0 d7 d6 d5 d4 d3 d2 d1 register address d15 24 d14d13d12d11d10 d9 d8
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c interface 17 january 10, 2012 4.1.2 three-wire mode in three-wire mode, cs is always at low level. when there is no oper- ation, sclk keeps at high level. t he start of a read or write operation is triggered if sclk is consistently low for at least 400 s. the subsequent read or write operation is similar to that in four-wire mode. refer to fig- ure-8 and figure-9 . figure-8 read sequence in three-wire mode figure-9 write sequen ce in three-wire mode cs sclk 10 123456789 11121314151617181920212223 register address 24 1234 low 400 s drive low sdi sdo a0 a6 a5 a4 a3 a2 a1 hign impedance d 15 don't care 16-bit data d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 0 d 1 don t care a6 a5 a4 high impedance low 400 s cs sclk sdi sdo 10 123456789 11121314151617181920212223 a0 a6 a5 a4 a3 a2 a1 16-bit data high impedance d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 register address d 14 d 15 24 d 13 d 12 d 11 d 10 d 9 d 8 1234 a6 a5 a4 don't care drive low low 400 s low 400 s don't care
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c interface 18 january 10, 2012 4.1.3 timeout and protection timeout occurs if sclk does not toggle for 6ms in both four-wire and three-wire modes. when timeout, the read or write operation is aborted. if there are more than 24 sclk cycles when cs is driven low in four- wire mode or between two starts in three-wire mode, writing operation is prohibited while normal reading oper ation can be completed by taking the first 24 sclk cycles as the valid ones. however, the reading result might not be the intended one. a read access to an invalid address returns all zero. a write access to an invalid address is discarded. table-9 and table-10 list the read or write result in different condi- tions. 4.2 warnout pin for fa tal error warning fatal error warning is raised through the warnout pin in two cases: checksum calibration error and voltage sag. calibration error the 90E21/22/23/24 performs diagnosis on a regular basis for impor- tant parameters such as calibration parameters and metering configura- tion. when checksum is not correct, the calerr[1:0] bits ( sysstatus , 01h) are set, and both the warnout pin and the irq pin are asserted. when checksum is not correct, the metering part does not work to pre- vent a large number of pulses during power-on or any abnormal situa- tion upon incorrect parameters. voltage sag voltage sag is detected when voltage is continuously below the volt- age sag threshold for one cycle which starts from any zero-crossing point. voltage threshold is configured by the sagth register (03h). refer to section 6.5 . when voltage sag occurs, the sagwarn bit ( sysstatus , 01h) is set and the warnout pin is asserted if the funcen register (02h) enables voltage sag warning through the warnout pin. this function helps reduce power-down detection circuit in system design. in addition, the method of judging voltage sag by detecting ac side voltage eliminates the influence of large capacitor in tr aditional rectifier circuit, and can detect voltage sag earlier. 4.3 low cost implementation in isolation with mcu the following functions can be achieved at low cost when the 90E21/ 22/23/24 is isolated from the mcu: spi: mcu can perform read and write operations through low speed optocoupler (e.g. nec2501) when the 90E21/22/23/24 is isolated from the mcu. the spi interface can be of 3-wire or 4-wire. energy pulses cfx: energy c an be accumulated by reading values in corresponding energy registers. cfx can also connect to the optocou- pler and the energy pulse light can be turned on by cfx. fatal error warnout: fatal error can be acquired by reading the cale rr[1:0] bits ( sysstatus , 01h). irq: irq interrupt can be acquired by reading the sysstatus register (01h). reset: the 90E21/22/23/24 is reset when ?789ah? is written to the software reset register ( softreset , 00h). table-9 read / write r esult in four-wire mode condition result operation timeout sclk cycles note 1 read/write status lastspidata register update read - note 2 >=24 normal read yes - note 2 <24 partial read no write no =24 normal write yes no !=24 no write no yes - no write no note 1: the number of sclk cycles when cs is driven low or the number of sclk cycles before timeout if any. note 2: '-' stands for don't care. table-10 read / write result in three-wire mode condition result operation timeout sclk cycles note 1 read/write status lastspidata register update read no >=24 note 2 normal read yes timeout after 24 cycles >24 normal read yes timeout before 24 cycles - note 3 partial read no timeout at 24 cycles =24 normal read yes write no =24 normal write yes no !=24 no write no yes - no write no note 1: the number of sclk cycles between 2 starts or the number of sclk cycles before timeout if any. note 2: there is no such case of less than 24 sclk cycles when there is no timeout in three-wire mode, because the first few sclk cycles in the next oper- ation is counted into this operation. in this case, data is corrupted. note 3: '-' stands for don't care.
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 19 january 10, 2012 5 register 5.1 register list table-11 register list register address register name read/write type functional description comment note 1 page status and special register 00h softreset w software reset p21 01h sysstatus r/c system status different for various chips note 2, note 3 p22 02h funcen r/w function enable different for various chips note 2 p23 03h sagth r/w voltage sag threshold p23 04h smallpmod r/w small-power mode p24 06h lastspidata r last read/write spi value p24 metering calibration and configuration register 20h calstart r/w calibration start command p25 21h plconsth r/w high word of pl_constant p25 22h plconstl r/w low word of pl_constant p26 23h lgain r/w l line calibration gain p26 24h lphi r/w l line calibration angle p26 25h ngain r/w n line calibration gain not applicable to the 90E21/22 note 3 p27 26h nphi r/w n line calibration angle not applicable to the 90E21/22 note 3 p27 27h pstartth r/w active startup power threshold p27 28h pnolth r/w active no-load power threshold p28 29h qstartth r/w reactive startup power threshold not applicable to the 90E21/23 note 2 p28 2ah qnolth r/w reactive no-load power threshold not applicable to the 90E21/23 note 2 p28 2bh mmode r/w metering mode configuration different for various chips note 2, note 3 p29 2ch cs1 r/w checksum 1 p31 measurement cali bration register 30h adjstart r/w measurement calibration start command p32 31h ugain r/w voltage rms gain p32 32h igainl r/w l line current rms gain p33 33h igainn r/w n line current rms gain not applicable to the 90E21/22 note 3 p33 34h uoffset r/w voltage offset p33 35h ioffsetl r/w l line current offset p34 36h ioffsetn r/w n line current offset not applicable to the 90E21/22 note 3 p34 37h poffsetl r/w l line active power offset p34 38h qoffsetl r/w l line reactive power offset not applicable to the 90E21/23 note 2 p35 39h poffsetn r/w n line active power offset not applicable to the 90E21/22 note 3 p35 3ah qoffsetn r/w n line reactive power offset not applicable to the 90E21/22/23 note 2, note 3 p35 3bh cs2 r/w checksum 2 p36 energy register 40h apenergy r/c forward active energy p37
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 20 january 10, 2012 41h anenergy r/c reverse active energy p37 42h atenergy r/c absolute active energy p38 43h rpenergy r/c forward (inductive) reactive energy not applicable to the 90E21/23 note 2 p38 44h rnenergy r/c reverse (capacitive) reactive energy not applicable to the 90E21/23 note 2 p39 45h rtenergy r/c absolute reactive energy not applicable to the 90E21/23 note 2 p39 46h enstatus r metering status different for various chips note 2, note 3 p40 measurement register 48h irms r l line current rms p41 49h urms r voltage rms p41 4ah pmean r l line mean active power p42 4bh qmean r l line mean reactive power not applicable to the 90E21/23 note 2 p42 4ch freq r voltage frequency p43 4dh powerf r l line power factor p43 4eh pangle r phase angle between voltage and l line current p43 4fh smean r l line mean apparent power p44 68h irms2 r n line current rms not applicable to the 90E21/22 note 3 p44 6ah pmean2 r n line mean active power not applicable to the 90E21/22 note 3 p45 6bh qmean2 r n line mean reactive power not applicable to the 90E21/22/23 note 2, note 3 p45 6dh powerf2 r n line power factor not applicable to the 90E21/22 note 3 p46 6eh pangle2 r phase angle between voltage and n line current not applicable to the 90E21/22 note 3 p46 6fh smean2 r n line mean apparent power not applicable to the 90E21/22 note 3 p47 note: 1. this register list shows all registers for the 90e24. 2. this register is related to reactive energy metering. part of this register is invalid for the 90E21/23 which does not have reactive metering. reading these registers always return 0000h and writing these registers always take no effect. 3. this register is related to n line metering. part of this register is invalid for the 90E21/22 which does not have n line me tering. reading these registers always return 0000h and writing these registers always have no effect. table-11 register list (continued) register address register name read/write type functional description comment note 1 page
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 21 january 10, 2012 5.2 status and special register softreset software reset address: 00h type: write default value: 0000h bit name description 15 - 0 softreset[15:0] software reset register. the 90E21/22/23/24 resets if only 789ah is written to this register. 15 14 13 12 11 10 9 8 softreset15 softreset14 softreset13 softreset12 softreset11 softreset10 softreset9 softreset8 76543210 softreset7 softreset6 softreset5 softreset4 s oftreset3 softreset2 softreset1 softreset0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 22 january 10, 2012 sysstatus system status address: 01h type: read/clear default value: 0000h bit name description 15 - 14 calerr[1:0] these bits indicate cs1 checksum status. 00: cs1 checksum correct (default) 11: cs1 checksum error. at the same time, the warnout pin is asserted. 13 - 12 adjerr[1:0] these bits indicate cs2 checksum status. 00: cs2 checksum correct (default) 11: cs2 checksum error. 11 - 8 - reserved. 7 lnchange this bit indicates whether there is any change of the metering line (l line and n line). 0: metering line no change (default) 1: metering line changed 6revqchq this bit indicates whether there is any change with the direction of reactive energy. 0: direction of reactive energy no change (default) 1: direction of reactive energy changed this status is enabled by the revqen bit( funcen , 02h). 5 revpchg this bit indicates whether there is any change with the direction of active energy. 0: direction of active energy no change (default) 1: direction of active energy changed this status is enabled by the revpen bit ( funcen , 02h). 4 - 2 - reserved. 1 sagwarn this bit indicates the voltage sag status. 0: no voltage sag (default) 1: voltage sag voltage sag is enabled by the sagen bit ( funcen , 02h). voltage sag status can also be reported by the warnout pin. it is enabled by the sagwo bit( funcen , 02h). 0- reserved. note: any of the above events will prompt the irq pin to be asserted, which can be supplied to external mcu as an interrupt. 15 14 13 12 11 10 9 8 calerr1 calerr0 adjerr1 adjerr0 - - - - 76543210 lnchange revqchg revpchg - - - sagwarn -
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 23 january 10, 2012 funcen function enable sagth voltage sag threshold address: 02h type: read/write default value: 000ch bit name description 15 - 6 - reserved. 5sagen this bit determines whether to enable the voltage sag interrupt. 0: disable (default) 1: enable 4sagwo this bit determines whether to enable voltage sag to be reported by the warnout pin. 0: disable (default) 1: enable 3revqen this bit determines whether to enable the direction change interrupt of reactive energy. 0: disable 1: enable (default) 2 revpen this bit determines whether to enable the direction change interrupt of active energy. 0: disable 1: enable (default) 1 - 0 - reserved. address: 03h type: read/write default value: 1d6ah bit name description 15 - 0 sagth[15:0] voltage sag threshold conf iguration. data format is xxx.xx. unit is v. the power-on value of sagth is 1d6ah, which is calculated by 22000*sqrt(2)*0.78/(4*ugain/32768) for details, please refer to idt application note an-641. 15 14 13 12 11 10 9 8 -------- 76543210 - - sagen sagwo revqen revpen - - 15 14 13 12 11 10 9 8 sagth15 sagth14 sagth13 sagth12 sagth11 sagth10 sagth9 sagth8 76543210 sagth7 sagth6 sagth5 sagth4 sagth3 sagth2 sagth1 sagth0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 24 january 10, 2012 smallpmod small-power mode lastspidata last read/write spi value address: 04h type: read/write default value: 0000h bit name description 15 - 0 smallpmod[15:0] small-power mode command. a987h: small-power mode. the relationship between the register value of l line and n line active/reactive power in small-power mode and normal mode is: power in normal mode = power in small-power mode *10*igain*ugain /2^42 others: normal mode. small-power mode is mainly used in the power offset calibration. address: 06h type: read default value: 0000h bit name description 15 - 0 lastspi- data[15:0] this register stores the data that is just read or written through the spi interface. refer to table-9 and table-10 . 15 14 13 12 11 10 9 8 smallpmod15 smallpmod14 smallpmod13 smallpmod12 smallpmod11 smallpmod10 smallpmod9 smallpmod8 76543210 smallpmod7 smallpmod6 smallpmod5 smallpmod4 smallpmod3 smallpmod2 smallpmod1 smallpmod0 15 14 13 12 11 10 9 8 lastspidata15 lastspidata14 lastspidata13 lastspidata12 lastspidata11 lastspidata10 lastspidata9 lastspidata8 76543210 lastspidata7 lastspidata6 lastspidata5 lastspidata4 lastspidata3 lastspidata2 lastspidata1 lastspidata0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 25 january 10, 2012 5.3 metering/ measure ment calibration and configuration 5.3.1 metering calibration and configuration register calstart calibration start command plconsth high word of pl_constant address: 20h type: read/write default value: 6886h bit name description 15 - 0 calstart[15:0] metering calibration start command: 6886h: power-on value. metering function is disabled. 5678h: metering calibration startup command. after 5678h is written to this register, registers 21h-2bh resume to their power- on values. the 90E21/22/23/24 starts to meter and output energy pulses regardless of the correctness of diagnosis. the calerr[1:0] bits ( sysstatus , 01h) are not set and the warnout/irq pins do not report any warning/interrupt. 8765h: check the correctness of the 21h-2bh registers. if correc t, normal metering. if not correct, metering function is disabl ed, the calerr[1:0] bits ( sysstatus , 01h) are set and the warnout/irq pins report warning/interrupt. others: metering function is disabled. the calerr[1:0] bits ( sysstatus , 01h) are set and the warnout/irq pins report warning/ interrupt. address: 21h type: read/write default value: 0015h bit name description 15 - 0 plconsth[15:0] the plconsth[15:0] and plconstl[15:0] bits are high word and low word of pl_constant respectively. pl_constant is a constant which is proportional to the sampling ratios of voltage and current, and inversely proportional to th e meter constant. pl_constant is a threshold for energy calculated inside the chip, i.e., energy larger than pl_constant will be accumulated in the corresponding energy registers and then output on cfx. it is suggested to set pl_constant as a multiple of 4 so as to double or redouble meter constant in low current state to save v er- ification time. note: plconsth takes effect after plconstl are configured. for details, please refer to idt application note an-641. 15 14 13 12 11 10 9 8 calstart15 calstart14 calstart13 calstart12 calstart11 calstart10 calstart9 calstart8 76543210 calstart7 calstart6 calstart5 calstart4 calstart3 calstart2 calstart1 calstart0 15 14 13 12 11 10 9 8 plconsth15 plconsth14 plconsth13 plconsth12 plconsth11 plconsth10 plconsth9 plconsth8 76543210 plconsth7 plconsth6 plconsth5 plconsth4 plconsth3 plconsth2 plconsth1 plconsth0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 26 january 10, 2012 plconstl low word of pl_constant lgain l line calibration gain lphi l line calibration angle address: 22h type: read/write default value: d174h bit name description 15 - 0 plconstl[15:0] the plconsth[15:0] and plconstl[15:0] bits are high word and low word of pl_constant respectively. it is suggested to set pl_constant as a multiple of 4. for details, please refer to idt application note an-641. address: 23h type: read/write default value: 0000h bit name description 15 - 0 lgain[15:0] l line calibration gain. for details, please refer to idt application note an-641. address: 24h type: read/write default value: 0000h bit name description 15 - 0 lphi[15:0] l line calibration phase angle. for details, please refer to idt application note an-641. 15 14 13 12 11 10 9 8 plconstl15 plconstl14 plconstl13 plconstl12 plconstl11 plconstl10 plconstl9 plconstl8 76543210 plconstl7 plconstl6 plconstl5 plconstl4 plconstl3 plconstl2 plconstl1 plconstl0 15 14 13 12 11 10 9 8 lgain15 lgain14 lgain13 lgain12 lgain11 lgain10 lgain9 lgain8 76543210 lgain7 lgain6 lgain5 lgain4 lgain3 lgain2 lgain1 lgain0 15 14 13 12 11 10 9 8 lphi15 - - - - - lphi9 lphi8 76543210 lphi7 lphi6 lphi5 lphi4 lphi3 lphi2 lphi1 lphi0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 27 january 10, 2012 ngain n line calibration gain nphi n line calibration angle pstartth active startup power threshold address: 25h type: read/write default value: 0000h bit name description 15 - 0 ngain[15:0] n line calibration gain. for details, please refer to idt application note an-641. address: 26h type: read/write default value: 0000h bit name description 15 - 0 nphi[15:0] n line calibration phase angle. for details, please refer to idt application note an-641. address: 27h type: read/write default value: 08bdh bit name description 15 - 0 pstartth[15:0] active startup power threshold. for details, please refer to idt application note an-641. 15 14 13 12 11 10 9 8 ngain15 ngain14 ngain13 ngain12 ngain11 ngain10 ngain9 ngain8 76543210 ngain7 ngain6 ngain5 ngain4 ngain3 ngain2 ngain1 ngain0 15 14 13 12 11 10 9 8 nphi15 - - - - - nphi9 nphi8 76543210 nphi7 nphi6 nphi5 nphi4 nphi3 nphi2 nphi1 nphi0 15 14 13 12 11 10 9 8 pstartth15 pstartth14 pstartth13 pstartth12 pstartth11 pstartth10 pstartth9 pstartth8 76543210 pstartth7 pstartth6 pstartth5 pstartth4 pstartth3 pstartth2 pstartth1 pstartth0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 28 january 10, 2012 pnolth active no-load power threshold qstartth reactive startup power threshold qnolth reactive no-load power threshold address: 28h type: read/write default value: 0000h bit name description 15 - 0 pnolth[15:0] active no-load power threshold. for details, please refer to idt application note an-641. address: 29h type: read/write default value: 0aech bit name description 15 - 0 qstartth[15:0] reactive startup power threshold. for details, please refer to idt application note an-641. address: 2ah type: read/write default value: 0000h bit name description 15 - 0 qnolth[15:0] reactive no-load power threshold. for details, please refer to idt application note an-641. 15 14 13 12 11 10 9 8 pnolth15 pnolth14 pnolth13 pnolth12 pnolth11 pnolth10 pnolth9 pnolth8 76543210 pnolth7 pnolth6 pnolth5 pnolth4 pnolth3 pnolth2 pnolth1 pnolth0 15 14 13 12 11 10 9 8 qstartth15 qstartth14 qstartth13 qstartth12 qstartth11 qstartth10 qstartth9 qstartth8 76543210 qstartth7 qstartth6 qstartth5 qstartth4 qstartth3 qstartth2 qstartth1 qstartth0 15 14 13 12 11 10 9 8 qnolth15 qnolth14 qnolth13 qnolth12 qnolth11 qnolth10 qnolth9 qnolth8 76543210 qnolth7 qnolth6 qnolth5 qnolth4 qnolth3 qnolth2 qnolth1 qnolth0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 29 january 10, 2012 mmode metering mode configuration address: 2bh type: read/write default value: 9422h bit name description 15 - 13 lgain[2:0] l line current gain, default value is ?100?. 12 - 11 ngain[1:0] n line current gain 00: 2 01: 4 10: 1 (default) 11: 1 10 lnsel this bit specifies metering as l line or n line when metering mode is set to flexible mode by mmd1 and mmd0 pins. 0: n line 1: l line (default) 9 - 8 dishpf[1:0] these bits configure the high filter pass (hpf) after adc. ther e are two first-order hpf in serial: hpf1 and hpf0. the config- uration are applicable to all channels: 7amod cf1 output for active power: 0: forward or reverse energy pulse output (default) 1: absolute energy pulse output 6rmod cf2 output for reactive power: 0: forward (inductive) or reverse (capacitive) energy pulse output (default) 1: absolute energy pulse output 15 14 13 12 11 10 9 8 lgain2 lgain1 lgain0 ngain1 ngain0 lnsel dishpf1 dishpf0 76543210 amod rmod zxcon1 zxcon0 pthresh3 pthresh2 pthresh1 pthresh0 lgain2 lgain1 lgain0 current channel gain 1xx 1 000 4 001 8 010 16 011 24 dishpf1 dishpf 0 hpf configuration 0 0 enable hpf1 and hpf0 (default) 0 1 enable hpf1, disable hpf0; 1 0 disable hpf1, enable hpf0; 1 1 disable hpf1 and hpf0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 30 january 10, 2012 5 - 4 zxcon[1:0] these bits configure zero-crossing mode. the zx pin outputs 5ms-width high level when voltage crosses zero. 00: positive zero-crossing 01: negative zero-crossing 10: all zero-crossing: both positive and negative zero-crossing (default) 11: no zero-crossing output 3 - 0 pthresh[3:0] these bits configure the l line and n line power difference threshold in anti-tampering mode. pthresh3 pthresh2 pthresh1 pthresh0 threshold 0000 12.5% 0 0 0 1 6.25% 0 0 1 0 3.125% (default) 0 0 1 1 1.5625% 0100 1% 0101 2% 0110 3% 0111 4% 1000 5% 1001 6% 1010 7% 1011 8% 1100 9% 1 1 0 1 10% 1110 11% 1 1 1 1 12%
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 31 january 10, 2012 cs1 checksum 1 address: 2ch type: read/write default value: 0000h bit name description 15 - 0 cs1[15:0] the cs1 register should be written after the 21h-2bh registers ar e written. suppose the high byte and the low byte of the 21h- 2bh registers are shown in below table. the calculatiion of the cs1 register is as follows: the low byte of 2ch register is: l 2c =mod( h 21 + h 22 +...+ h 2b + l 21 + l 22 +...+ l 2b , 2^8) the high byte of 2ch register is: h 2c = h 21 xor h 22 xor ... xor h 2b xor l 21 xor l 22 xor ... xor l 2b for 90E21/22/23, a part of registers are not used. these registers can be dealed as 0000h in cs calculation. the 90E21/22/23/24 calculates cs1 regularly. if the value of the cs1 register and the calculation by the 90E21/22/23/24 is diff er- ent when calstart =8765h, the calerr[1:0] bits ( sysstatus , 01h) are set and the warnout and irq pins are asserted. note: the readout value of the cs1 register is the calculation by the 90E21/22/23/24, which is different from what is written. 15 14 13 12 11 10 9 8 cs1_15 cs1_14 cs1_13 cs1_12 cs1_11 cs1_10 cs1_9 cs1_8 76543210 cs1_7 cs1_6 cs1_5 cs1_4 cs1_3 cs1_2 cs1_1 cs1_0 register address high byte low byte 21h h 21 l 21 22h h 22 l 22 23h h 23 l 23 24h h 24 l 24 25h h 25 l 25 26h h 26 l 26 27h h 27 l 27 28h h 28 l 28 29h h 29 l 29 2ah h 2a l 2a 2bh h 2b l 2b
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 32 january 10, 2012 5.3.2 measurement calibration register adjstart measurement calibration start command ugain voltage rms gain address: 30h type: read/write default value: 6886h bit name description 15 - 0 adjstart[15:0] measurement calibration start command 6886h: power-on value. no measurement. 5678h: measurement calibration startup command. after 5678h is wr itten to this register, registers 31h-3ah resume to their power-on values. the 90E21/22/23/24 starts to measure regardl ess of the correctness of diagnosis. the adjerr[1:0] bits ( sysstatus , 01h) are not set and the irq pin does not report any interrupt. 8765h: check the correctness of the 31h-3ah registers. if corre ct, normal measurement. if not correct, measurement function is disabled, the adjerr[1:0] bits ( sysstatus , 01h) are set and the irq pin reports interrupt. others: no measurement. the adjerr[1:0] bits ( sysstatus , 01h) are set and the irq pin reports interrupt. address: 31h type: read/write default value: 6720h bit name description 15 - 0 ugain[15:0] voltage rms gain. for details, please refer to idt application note an-641. note: the ugain15 bit should only be '0' 15 14 13 12 11 10 9 8 adjstart15 adjstart14 adjstart13 adjstart12 adjstart11 adjstart10 adjstart9 adjstart8 76543210 adjstart7 adjstart6 adjstart5 adjstart4 adjstart3 adjstart2 adjstart1 adjstart0 15 14 13 12 11 10 9 8 ugain15 ugain14 ugain13 ugain12 ugain11 ugain10 ugain9 ugain8 76543210 ugain7 ugain6 ugain5 ugain4 ugain3 ugain2 ugain1 ugain0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 33 january 10, 2012 igainl l line current rms gain igainn n line current rms gain uoffset voltage offset address: 32h type: read/write default value: 7a13h bit name description 15 - 0 igainl[15:0] l line current rms gain, for details, please refer to idt application note an-641. address: 33h type: read/write default value: 7530h bit name description 15 - 0 igainn[15:0] n line current rms gain. for details, please refer to idt application note an-641. address: 34h type: read/write default value: 0000h bit name description 15 - 0 uoffset[15:0] voltage offset. for calculation method, please refer to idt application note an-641. 15 14 13 12 11 10 9 8 igainl15 igainl14 igainl13 igainl12 igainl11 igainl10 igainl9 igainl8 76543210 igainl7 igainl6 igainl5 igainl4 igainl3 igainl2 igainl1 igainl0 15 14 13 12 11 10 9 8 igainn15 igainn14 igainn13 igainn12 igainn11 igainn10 igainn9 igainn8 76543210 igainn7 igainn6 igainn5 igainn4 igainn3 igainn2 igainn1 igainn0 15 14 13 12 11 10 9 8 uoffset15 uoffset14 uoffset13 uoffset12 uoffset11 uoffset10 uoffset9 uoffset8 76543210 uoffset7 uoffset6 uoffset5 uoffset4 uoffset3 uoffset2 uoffset1 uoffset0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 34 january 10, 2012 ioffsetl l line current offset ioffsetn n line current offset poffsetl l line active power offset address: 35h type: read/write default value: 0000h bit name description 15 - 0 ioffsetl[15:0] l line current offset. for calculation method, please refer to idt application note an-641. address: 36h type: read/write default value: 0000h bit name description 15 - 0 ioffsetn[15:0] n line current offset. for calculation method, please refer to idt application note an-641. address: 37h type: read/write default value: 0000h bit name description 15 - 0 poffsetl[15:0] l line active power offset. complement, msb is the sign bit. for calculation method, please refer to idt application note an-641. 15 14 13 12 11 10 9 8 ioffsetl15 ioffsetl14 ioffsetl13 ioffsetl12 ioffsetl11 ioffsetl10 ioffsetl9 ioffsetl8 76543210 ioffsetl7 ioffsetl6 ioffsetl5 ioffsetl4 ioffsetl3 ioffsetl2 ioffsetl1 ioffsetl0 15 14 13 12 11 10 9 8 ioffsetn15 ioffsetn14 ioffsetn13 ioffsetn12 ioffsetn11 ioffsetn10 ioffsetn9 ioffsetn8 76543210 ioffsetn7 ioffsetn6 ioffsetn5 ioffsetn4 ioffsetn3 ioffsetn2 ioffsetn1 ioffsetn0 15 14 13 12 11 10 9 8 poffsetl15 poffsetl14 poffsetl13 poffsetl12 poffsetl11 poffsetl10 poffsetl9 poffsetl8 76543210 poffsetl7 poffsetl6 poffsetl5 poffsetl4 poffsetl3 poffsetl2 poffsetl1 poffsetl0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 35 january 10, 2012 qoffsetl l line reactive power offset poffsetn n line active power offset qoffsetn n line reactive power offset address: 38h type: read/write default value: 0000h bit name description 15 - 0 qoffsetl[15:0] l line reactive power offset. complement, msb is the sign bit. for calculation method, please refer to idt application note an-641. address: 39h type: read/write default value: 0000h bit name description 15 - 0 poffsetn[15:0] n line active power offset. complement, msb is the sign bit. for calculation method, please refer to idt application note an-641. address: 3ah type: read/write default value: 0000h bit name description 15 - 0 qoffsetn[15:0] n line reactive power offset. complement, msb is the sign bit. for calculation method, please refer to idt application note an-641. 15 14 13 12 11 10 9 8 qoffsetl15 qoffsetl14 qoffsetl13 qoffsetl12 qoffsetl11 qoffsetl10 qoffsetl9 qoffsetl8 76543210 qoffsetl7 qoffsetl6 qoffsetl5 qoffsetl4 qoffsetl3 qoffsetl2 qoffsetl1 qoffsetl0 15 14 13 12 11 10 9 8 poffsetn15 poffsetn14 poffsetn13 poffsetn12 poffsetn11 poffsetn10 poffsetn9 poffsetn8 76543210 poffsetn7 poffsetn6 poffsetn5 poffsetn4 poffsetn3 poffsetn2 poffsetn1 poffsetn0 15 14 13 12 11 10 9 8 qoffsetn15 qoffsetn14 qoffsetn13 qoffsetn12 qoffsetn11 qoffsetn10 qoffsetn9 qoffsetn8 76543210 qoffsetn7 qoffsetn6 qoffsetn5 qoffsetn4 qoffsetn3 qoffsetn2 qoffsetn1 qoffsetn0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 36 january 10, 2012 cs2 checksum 2 address: 3bh type: read/write default value: 0000h bit name description 15 - 0 cs2[15:0] the cs2 register should be written after the 31h-3ah registers ar e written. suppose the high byte and the low byte of the 31h- 3ah registers are shown in below table. the calculatiion of the cs2 register is as follows: the low byte of 3bh register is: l 3b =mod( h 31 + h 32 +...+ h 3a + l 31 + l 32 +...+ l 3a , 2^8) the high byte of 3bh register is: h 3b = h 31 xor h 32 xor ... xor h 3a xor l 31 xor l 32 xor ... xor l 3a for 90E21/22/23, a part of registers are not used. these registers can be dealed as 0000h in cs calculation. the 90E21/22/23/24 calculates cs2 regularly. if the value of the cs2 register and the calculation by the 90E21/22/23/24 is diff er- ent when adjstart =8765h, the adjerr[1:0] bits ( sysstatus , 01h) are set. note: the readout value of the cs2 register is the calculation by the 90E21/22/23/24, which is different from what is written. 15 14 13 12 11 10 9 8 cs2_15 cs2_14 cs2_13 cs2_12 cs2_11 cs2_10 cs2_9 cs2_8 76543210 cs2_7 cs2_6 cs2_5 cs2_4 cs2_3 cs2_2 cs2_1 cs2_0 register address high byte low byte 31h h 31 l 31 32h h 32 l 32 33h h 33 l 33 34h h 34 l 34 35h h 35 l 35 36h h 36 l 36 37h h 37 l 37 38h h 38 l 38 39h h 39 l 39 3ah h 3a l 3a
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 37 january 10, 2012 5.4 energy register theory of energy registers the internal energy resolution is 0.01 pulse. within 0.01 pulse, forward and reverse energy are counteracted. when energy exceeds 0.01 pulse, the respec- tive forward/reserve energy is increased. the forward and reverse energy are not counteracted in absolute energy registers. take the example of active energy, suppose: t0: forward energy is 12.34 pulses and reverse energy is 1.23 pulses; from t0 to t1: 0.005 forward pulse appeared from t1 to t2: 0.004 reverse pulse appeared from t2 to t3: 0.003 reverse pulse appeared when forward/reverse energy or absolute energy reaches 0.1 pulse, the respec- tive register is updated. when forward/reverse energy or absolute energy reaches 1 pulse, cfx pins output pulse and the revp/revq bits ( enstatus , 46h) are updated. absolute energy might be more than the sum of forward and reverse energies. if ?consistency? is required between absolute energy and forward/reverse energy in system application, absolute energy can be obtained by calculating the read- out of the forward and reverse energy registers. apenergy forward active energy anenergy reverse active energy t0 t1 t2 t3 forward active pulse 12.34 12.345 12.341 12.34 reserve active pulse 1.23 1.23 1.23 1.232 absolute active pulse 13.57 13.575 13.579 13.582 address: 40h type: read/clear default value: 0000h bit name description 15 - 0 apenergy[15:0] forward active energy; cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. address: 41h type: read/clear default value: 0000h bit name description 15 - 0 anenergy[15:0] reverse active energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. 15 14 13 12 11 10 9 8 apenergy15 apenergy14 apenergy13 apenergy12 apenergy11 apenergy10 apenergy9 apenergy8 76543210 apenergy7 apenergy6 apenergy5 apenergy4 apenergy3 apenergy2 apenergy1 apenergy0 15 14 13 12 11 10 9 8 anenergy15 anenergy14 anenergy13 anenergy12 a nenergy11 anenergy10 anenergy9 anenergy8 76543210 anenergy7 anenergy6 anenergy5 anenergy4 a nenergy3 anenergy2 anenergy1 anenergy0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 38 january 10, 2012 atenergy absolute active energy rpenergy forward (inductive) reactive energy address: 42h type: read/clear default value: 0000h bit name description 15 - 0 atenergy[15:0] absolute active energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. address: 43h type: read/clear default value: 0000h bit name description 15 - 0 rpenergy[15:0] forward (inductive) reactive energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. 15 14 13 12 11 10 9 8 atenergy15 atenergy14 atenergy13 atenergy12 atenergy11 atenergy10 atenergy9 atenergy8 76543210 atenergy7 atenergy6 atenergy5 atenergy4 atenergy3 atenergy2 atenergy1 atenergy0 15 14 13 12 11 10 9 8 rpenergy15 rpenergy14 rpenergy13 rpenergy12 rpenergy11 rpenergy10 rpenergy9 rpenergy8 76543210 rpenergy7 rpenergy6 rpenergy5 rpenergy4 r penergy3 rpenergy2 rpenergy1 rpenergy0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 39 january 10, 2012 rnenergy reverse (capacitive) reactive energy rtenergy absolute reactive energy address: 44h type: read/clear default value: 0000h bit name description 15 - 0 rnenergy[15:0] reverse (capacitive) reactive energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. address: 45h type: read/clear default value: 0000h bit name description 15 - 0 rtenergy[15:0] absolute reactive energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. 15 14 13 12 11 10 9 8 rnenergy15 rnenergy14 rnenergy13 rnenergy1 2 rnenergy11 rnenergy10 rnenergy9 rnenergy8 76543210 rnenergy7 rnenergy6 rnenergy5 rnenergy4 rnenergy3 rnenergy2 rnenergy1 rnenergy0 15 14 13 12 11 10 9 8 rtenergy15 rtenergy14 rtenergy13 rtenergy12 rtenergy11 rtenergy10 rtenergy9 rtenergy8 76543210 rtenergy7 rtenergy6 rtenergy5 rtenergy4 rtenergy3 rtenergy2 rtenergy1 rtenergy0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 40 january 10, 2012 enstatus metering status address: 46h type: read default value after power on: c800h bit name description 15 qnoload this bit indicates whether the chip is in reactive no-load status. 0: not reactive no-load state 1: reactive no-load state 14 pnoload this bit indicates whether the 90E21/22/23/24 is in active no-load status. 0: not active no-load state 1: active no-load state 13 revq this bit indicates the direction of the last cf2 (reactive output). 0: reactive forward 1: reactive reverse note: this bit is always '0' when the cf2 output is configured to be absolute energy. 12 revp this bit indicates the direction of the last cf1 (active output). 0: active forward 1: active reverse note: this bit is always '0' when the cf1 output is configured to be absolute energy. 11 lline this bit indicates the current metering line in anti-tampering mode. 0: n line 1: l line 10 - 2 - reserved. 1 - 0 lnmode[1:0] these bits indicate the configuration of mmd1 and mmd0 pins. their relationship is as follows: 15 14 13 12 11 10 9 8 qnoload pnoload revq revp lline - - - 76543210 - - - - - - lnmode1 lnmode0 mmd1 mmd0 lnmod1 lnmod0 l/n metering mode 0 0 0 0 anti-tampering mode (larger power) 0 1 0 1 l line mode (fixed l line) 1 0 1 0 l+n mode (applicable for single-phase three-wire system) 1 1 1 1 flexible mode (line specified by the lnsel bit ( mmode , 2bh))
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 41 january 10, 2012 5.5 measurement register irms l line current rms urms voltage rms address: 48h type: read default value: 0000h bit name description 15 - 0 irms[15:0] l line current rms. data format is xx.xxx, whic h corresponds to 0 ~ 65.535a. for cases when the current exceeds 65.535a, it is suggested to be handled by mcu in application. for example, the register value can be calibrated to 1/2 of the actual value during calibration, then multiplied by 2 in application. address: 49h type: read default value: 0000h bit name description 15 - 0 urms[15:0] voltage rms. data format is xxx.xx, whic h corresponds to 0 ~ 655.35v. 15 14 13 12 11 10 9 8 irms15 irms14 irms13 irms12 irms11 irms10 irms9 irms8 76543210 irms7 irms6 irms5 irms4 irms3 irms2 irms1 irms0 15 14 13 12 11 10 9 8 urms15 urms14 urms13 urms12 urms11 urms10 urms9 urms8 76543210 urms7 urms6 urms5 urms4 urms3 urms2 urms1 urms0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 42 january 10, 2012 pmean l line mean active power qmean l line mean reactive power address: 4ah type: read default value: 0000h bit name description 15 - 0 pmean[15:0] l line mean active power. complement, msb is the sign bit. data format is xx.xxx, which corresponds to -32.768~+32.768kw. if current is specially handle by mcu, the power of the 90E21/22/23/24 and the actual power have the same multiple relationship as the current. address: 4bh type: read default value: 0000h bit name description 15 - 0 qmean[15:0] l line mean reactive power. complement, msb is the sign bit. data format is xx.xxx, which corresponds to -32.768~+32.768kvar. if current is specially handled by mcu, the power of the 90e22/24 and the actual power have the same multiple relationship as the current. 15 14 13 12 11 10 9 8 pmean15 pmean14 pmean13 pmean12 pmean11 pmean10 pmean9 pmean8 76543210 pmean7 pmean6 pmean5 pmean4 pmean3 pmean2 pmean1 pmean0 15 14 13 12 11 10 9 8 qmean15 qmean14 qmean13 qmean12 qmean11 qmean10 qmean9 qmean8 76543210 qmean7 qmean6 qmean5 qmean4 qmean3 qmean2 qmean1 qmean0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 43 january 10, 2012 freq voltage frequency powerf l line power factor pangle phase angle between voltage and l line current address: 4ch type: read default value: 0000h bit name description 15 - 0 freq[15:0] voltage frequency. data format is xx.xx. frequency measurement range is 45.00~65.00hz. for example, 1388h corresponds to 50.00hz. address: 4dh type: read default value: 0000h bit name description 15 - 0 powerf[15:0] l line power factor. signed, msb is the sign bit. data format is x.xxx. power factor range: -1.000~+1.000. for example, 03e8h corresponds to the power factor of 1.000, and 83e8h corresponds to the power factor of -1.000. address: 4eh type: read default value: 0000h bit name description 15 - 0 pangle[15:0] l line voltage current angle. signed, msb is the sign bit. data format is xxx.x. angle range: -180.0~+180.0 degree. 15 14 13 12 11 10 9 8 freq15 freq14 freq13 freq12 freq11 freq10 freq9 freq8 76543210 freq7 freq6 freq5 freq4 freq3 freq2 freq1 freq0 15 14 13 12 11 10 9 8 powerf15 powerf14 powerf13 powerf12 powerf11 powerf10 powerf9 powerf8 76543210 powerf7 powerf6 powerf5 powerf4 powerf3 powerf2 powerf1 powerf0 15 14 13 12 11 10 9 8 pangle15 pangle14 pangle13 pangle12 pangle11 pangle10 pangle9 pangle8 76543210 pangle7 pangle6 pangle5 pangle4 pangle3 pangle2 pangle1 pangle0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 44 january 10, 2012 smean l line mean apparent power irms2 n line current rms address: 4fh type: read default value: 0000h bit name description 15 - 0 smean[15:0] l line mean apparent power. complement, msb is always '0'. data format is xx.xxx, whic h corresponds to 0~+32.767kva. if current is specially handled by mcu, the power of the 90E21/22/23/24 and the actual power have the same multiple relation- ship as the current. address: 68h type: read default value: 0000h bit name description 15 - 0 irms2[15:0] n line current rms. data format is xx.xxx, which corresponds to 65.535a. for cases when the current exceeds 65.535a, it is suggested to be handled by mcu in application. for example, the register value can be calibrated to 1/2 of the actual value during calibration, then multiplied by 2 in application. 15 14 13 12 11 10 9 8 smean15 smean14 smean13 smean12 smean11 smean10 smean9 smean8 76543210 smean7 smean6 smean5 smean4 smean3 smean2 smean1 smean0 15 14 13 12 11 10 9 8 irms2_15 irms2_14 irms2_13 irms2_12 irms2_11 irms2_10 irms2_9 irms2_8 76543210 irms2_7 irms2_6 irms2_5 irms2_4 irms2_3 irms2_2 irms2_1 irms2_0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 45 january 10, 2012 pmean2 n line mean active power qmean2 n line mean reactive power address: 6ah type: read default value: 0000h bit name description 15 - 0 pmean2[15:0] n line mean active power. complement, msb is the sign bit. data format is xx.xxx, which corresponds to -32.768~+32.767kw. if current is specially handled by mcu, the power of the 90E21/22/23/24 and the actual power have the same multiple relation- ship as the current. address: 6bh type: read default value: 0000h bit name description 15 - 0 qmean2[15:0] n line mean reactive power. complement, msb is the sign bit. data format is xx.xxx, which corresponds to -32.768~+32.767kvar. if current is specially handled by mcu, the power of 90e22/24 and the actual power have the same multiple relationship as the current. 15 14 13 12 11 10 9 8 pmean2_15 pmean2_14 pmean2_13 pmean2_12 pmean2_11 pmean2_10 pmean2_9 pmean2_8 76543210 pmean2_7 pmean2_6 pmean2_5 pmean2_4 pmean2_3 pmean2_2 pmean2_1 pmean2_0 15 14 13 12 11 10 9 8 qmean2_15 qmean2_14 qmean2_13 qmean2_12 qmean2_11 qmean2_10 qmean2_9 qmean2_8 76543210 qmean2_7 qmean2_6 qmean2_5 qmean2_4 qmean2_3 qmean2_2 qmean2_1 qmean2_0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 46 january 10, 2012 powerf2 n line power factor pangle2 phase angle between voltage and n line current address: 6dh type: read default value: 0000h bit name description 15 - 0 powerf2[15:0] n line power factor. signed, msb is the sign bit. data format is x.xxx. power factor range: -1.000~+1.000. for example, 03e8h corresponds to the power factor of 1.000, and 83e8h corresponds to the power factor of -1.000. address: 6eh type: read default value: 0000h bit name description 15 - 0 pangle2[15:0] n line voltage current angle signed, msb is the sign bit. data format is xxx.x. angle range: -180.0~+180.0 degree. 15 14 13 12 11 10 9 8 powerf2_15 powerf2_14 powerf2_13 powerf2_12 powerf2_11 powerf2_10 powerf2_9 powerf2_8 76543210 powerf2_7 powerf2_6 powerf2_5 powerf2_4 powerf2_3 powerf2_2 powerf2_1 powerf2_0 15 14 13 12 11 10 9 8 pangle2_15 pangle2_14 pangle2_13 pangle2_12 pangle2_11 pangle2_10 pangle2_9 pangle2_8 76543210 pangle2_7 pangle2_6 pangle2_5 pangle2_4 pangle2_3 pangle2_2 pangle2_1 pangle2_0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c register 47 january 10, 2012 smean2 n line mean apparent power address: 6fh type: read default value: 0000h bit name description 15 - 0 smean2[15:0] n line mean apparent power complement, msb is always '0'. data format is xx.xxx, whic h corresponds to 0~+32.767kva. if current is specially handled by mcu, the power of 90E21/22/23/24 and the actual power have the same multiple relationship as the current. 15 14 13 12 11 10 9 8 smean2_15 smean2_14 smean2_13 smean2_12 smean2_11 smean2_10 smean2_9 smean2_8 76543210 smean2_7 smean2_6 smean2_5 smean2_4 smean2_3 smean2_2 smean2_1 smean2_0
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c electrical specification 48 january 10, 2012 6 electrical specification 6.1 electrical specification parameters and description min. typical max. unit test conditions and comments accuracy dc power supply rejection ratio (psrr) 0.1 % vdd=3.3v 0.3v, 100hz, i=5a, v=220v, l line shunt resistor 150 ? , n line ct 1000:1, sampling resistor 4.8 ? ac power supply rejection ratio (psrr) 0.1 % vdd=3.3v superimposes 400mvrms, 100hz sinu- soidal signal, i=5a, v=220v, l line shunt resistor 150 ? , n line ct 1000:1, sampling resistor 4.8 ? active energy error (dynamic range 5000:1) 0.1 % l line current gain is ?24?; n line current gain is ?1? channel characteristics sampling frequency 8khz l line current channel equivalent input noise 19.1 single side band noise (measured at 50hz, and pga gain is ?24?) n line current channel equivalent input noise 458.4 single side band noise (measured at 50hz, and pga gain is ?1?) voltage channel equivalent input noise 458.4 single side band noise (measured at 50hz, and pga gain is ?1?) total harmonic distortion for each channel 80 db 25c, pga gain is ?1?, 500mvrms input reactive energy metering bandwidth 4 khz active energy metering bandwidth 4 khz irms and vrms measurement bandwidth 4 khz measurement error 0.5 % analog input l line current channel differential input 5 25m vrms pga gain is ?24? 7.5 37.5m pga gain is ?16? 15 75m pga gain is ?8? 30 150m pga gain is ?4? 120 600m pga gain is ?1? n line current channel differential input 30 150m vrms pga gain is ?4? 60 300m pga gain is ?2? 120 600m pga gain is ?1? voltage channel differential input 120 600m vrms pga gain is ?1? l line current channel input impedance 1 k ? n line current channel input impedance 50 k ? voltage channel input impedance 50 k ? l line current channel dc offset 10 mv pga gain is ?24? n line current channel dc offset 10 mv pga gain is ?1? voltage channel dc offset 10 mv pga gain is ?1? reference on-chip reference (90E21/22/23/24) 1.398 1.417 1.440 v reference voltage test mode reference voltage temperature coefficient 15 40 ppm/c clock crystal or external clock 8.192 mhz the accuracy of crystal or external clock is 100 ppm spi interface spi interface bit rate 200 160k bps pulse width cfx pulse width 80 ms if t 160 ms, width=80ms; if t<160 ms, width = 0.5t. refer to section 6.6 esd machine model (mm) 400 v jesd22-a115 charged device model (cdm) 1000 v jesd22-c101 hz / nv hz / nv hz / nv
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c electrical specification 49 january 10, 2012 human body model (hbm) 4000 v jesd22-a114 latch up 100 ma jesd78a latch up 4.95 v jesd78a operating conditions avdd, analog power supply 2.8 3.3 3.6 v metering precision guaranteed within 3.0v~3.6v. dvdd, digital power supply 2.8 3.3 3.6 v metering precision guaranteed within 3.0v~3.6v. i avdd , analog current (90E21/22) 3.00 ma l line current channel and voltage channel are open i avdd , analog current (90e23/24) 3.75 ma l line/ n line current channel and voltage channel are open i dvdd , digital current 2.75 ma vdd=3.3v dc characteristics digital input high level (all digital pins except osci) 2.0 vdd+2.6 v vdd=3.3v 10%, digital input high level (osci) 2.0 vdd+0.3 v vdd=3.3v 10% digital input low level 0.8 v vdd=3.3v 10% digital input leakage current 1 a vdd=3.6v, vi=vdd or gnd digital output low level (cf1, cf2) 0.4 v vdd=3.3v, i ol =10ma digital output low level (irq, warnout, zx, sdo) 0.4 v vdd=3.3v, i ol =5ma digital output high level (cf1, cf2) 2.4 v vdd=3.3v, i oh =-10ma digital output high level (irq, warnout, zx, sdo) 2.4 v vdd=3.3v, i oh =-5ma digital output low level (osco) 0.4 v vdd=3.3v, i ol =1ma digital output high level (osco) 2.4 v vdd=3.3v, i oh =-1ma
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c electrical specification 50 january 10, 2012 6.2 spi interface timing the spi interface timing is as shown in figure-10, figure-11 and table-12. figure-10 4-wire spi timing diagram figure-11 3-wire spi timing diagram table-12 spi timing specification symbol description min. typical max. unit t csh note 1 minimum cs high level time 30t note 2 +10 ns t css note 1 cs setup time 3t+10 ns t csd note 1 cs hold time 30t+10 ns t cld note 1 clock disable time 1t ns t clh clock high level time 30t+10 ns t cll clock low level time 16t+10 ns t dis data setup time 3t+10 ns t dih data hold time 22t+10 ns cs sclk sdi sdo t csh t css high impedance high impedance t csd t clh t cll t dis t dih t pd t df valid input valid output t cld t dw sclk sdi sdo high impedance high impedance t clh t cll t dis t dih t pd valid input valid output t dw
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c electrical specification 51 january 10, 2012 6.3 power on reset timing figure-12 power on reset timing diagram 6.4 zero-cross ing timing figure-13 zero-cross ing timing diagram t dw minimum data width 30t+10 ns t pd output delay 14t 15t+20 ns t df note 1 output disable time 16t+20 ns note: 1. not applicable for three-wire spi. 2. t means sclk cycle. t=122ns. (typical value for four-wire spi) table-12 spi timing specification (continued) table-13 power on reset specification symbol description min. typical max. unit v h power on trigger voltage 2.47 2.6 2.73 v v l power off trigger voltage 2.185 2.3 2.415 v v h -v l hysteretic voltage difference 0.285 0.3 0.315 v t 1 delay time after power on 5 ms t 2 delay time after power off 10 s dvdd reset t 1 v h t 2 v l zx (positive zero-crossing) zx (negative zero-crossing) zx (all zero-crossing) t zx t d v
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c electrical specification 52 january 10, 2012 6.5 voltage sag timing figure-14 voltage sag timing diagram 6.6 pulse output figure-15 output pulse width table-14 zero-crossing specification symbol description min. typical max. unit t zx high level width 5 ms t d delay time 0.5 ms table-15 voltage sag specification symbol description min. typical max. unit t d delay time 0.5 ms voltage sag threshold warnout irq t d v voltage sag threshold cfx t p =80ms t p =0.5t t 160ms 10ms t<160ms t p =5ms if t<10ms, force t=10ms
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c electrical specification 53 january 10, 2012 6.7 absolute maximum rating parameter maximum limit relative voltage between avdd and agnd -0.3v~3.7v relative voltage between dvdd and dgnd -0.3v~3.7v analog input voltage (i1p, i1n, i2p, i2n, vp, vn) -1v~vdd digital input voltage -0.3v~vdd+2.6v operating temperature range -40~85 c maximum junction temperature 150 c package type thermal resistance ja unit condition green ssop28 note 1 63.2 c/w no airflow note 1: refer to http://www.idt.com/package/pyg28 .
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c 54 january 10, 2012 package dimensions
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c 55 january 10, 2012
90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c 56 january 10, 2012
for tech support: 86-21-64958900 email:powermeterhelp@idt.com 57 90E21/22/23/24 single-phase high-perfo rmance wide-span energy metering i c corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com for sales: 86-21-64958900 idt and the idt logo are trademarks of integrated device technology, inc. 57 ordering information datasheet document history 09/02/2010 pg. 16 11/02/2010 pg. 37, 40 12/13/2010 pg. 6 , 10, 48, 52 12/27/2010 pg. 48 03/22/2011 pg. 53 01/10/2012 pg. 48, 52, 54, 55, 56 xxxxx xxx x device type i temperature range 90E21 industry (-40 to +85 ) single-phase high-performance wide-span energy metering ic pyg green ssop28 90e22 90e23 90e24 package

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